(China (Mainland))
Product Summary
The ISPLSI5384VA is an In-System Programmable 3.3V SuperWIDE High Density PLD. The ISPLSI5384VA is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the ISPLSI5384VA.
Parametrics
ISPLSI5384VA absolute maximum ratings: (1)Supply Voltage Vcc:-0.5 to +5.4V; (2)Input Voltage Applied:-0.5 to +5.6V; (3)Tri-Stated Output Voltage Applied:-0.5 to +5.6V; (4)Storage Temperature:-65 to 150℃; (5)Case Temp. with Power Applied:-55 to 125℃; (6)Max. Junction Temp. (TJ) with Power Applied:150℃.
Features
ISPLSI5384VA features: (1)3.3V Power Supply; (2)User Selectable 3.3V/2.5V I/O; (3)18,000 PLD Gates / 384 Macrocells; (4)Up to 288 I/O Pins; (5)384 Registers; (6)High-Speed Global Interconnect; (7)SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance; (8)SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.; (9)PCB Efficient Ball Grid Array (BGA) Package Options; (10)Superior Quality of Results; (11)Tightly Integrated with Leading CAE Vendor Tools; (12)Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER; (13)PC and UNIX Platforms; (14)Enhanced Pin-Locking Architecture with Single-Level Global Routing Pool and SuperWIDE GLBs; (15)Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell; (16)Macrocells Support Concurrent Combinatorial and Registered Functions; (17)Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable.
Diagrams
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ispLSI 1016-60LT44 |
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